Abstract
An 8-bit asynchronous single-ended Successive Approximation Register
(SAR) Analog-to-Digital Converter (ADC) for the realization of a
perovskite photovoltaic (PV) sensing application is presented. Various
techniques have been proposed to enhance speed and power efficiency. A
bootstrap transmission gate-based sample and hold circuit is proposed to
improve sampling linearity and reduce power consumption. The sample and
hold circuit is configured to operate at a 90% duty cycle, hence,
giving it enough time for the conversion. A two-stage latch dynamic
comparator is implemented to ensure high-speed and low power
consumption. The SAR ADC also implements an asynchronous SAR logic
block, controlled by an internal clock, which eliminates the need for an
external clock. The proposed SAR ADC was designed in a UMC 180nm CMOS
technology. The SAR ADC is tested with a sinusoidal analog input of 500
mV at 10 kHz frequency and a 4 MHz input clock frequency. The SAR ADC
consumes a power of 2.67 mW at a supply of 1.5 V. The proposed ADC is an
important unit for application in the fast growing perovskite-based PV
industry.