A 64-Channel sub-1nC Charge-balanced Stimulator IC for Seizure
Suppression
Seungah Lee, Byeongseol Kim and Joonsung Bae
We present a 64-channel implantable neural stimulator with sub-nC charge
balanced current stimulation for seizure suppression applications. The
regulated cascode current driver achieves almost full VDD compliance
voltage range. A passive charge balancing by shorting working and
reference electrodes with a bootstrapped switch keeps the residual
charge level within a safe limit, enabling faster-switching operation.
The stimulation parameters, such as current pulse width, channel
activation, activation frequency, and current amplitude, are highly
reconfigurable and adjusted through the SPI interface. Significantly,
the current amplitude can be varied from 1µA to 1.8 mA. As a result, the
proposed neural stimulator fabricated with a 0.18µm standard CMOS
process effectively suppresses seizures within a safe limit with a
residual charge of less than 1nC through the in-vivo test.
Introduction: Epilepsy is a brain disease in which paralysis of
brain function occurs repeatedly due to transient over-excitation of
brain nerve cells, which is the second most common chronic disease of
the nervous system after headaches. Electrical brain stimulation is
increasingly used in medication-resistant seizure therapy [1].
In the electrical current stimulator, once the bi-phasic current is
injected from the working electrode to the reference electrode, the
voltage level of the working electrode fluctuates according to the
electrode and tissue impedance. Therefore, a high compliance voltage is
required to deliver an applicable amount of charge to the tissue
regardless of the amplitude of the stimulation current. Conventional
current mode stimulator circuits exploit the high-voltage CMOS
technology to achieve a high compliance voltage of the stimulator
[2,3], which has significant disadvantages in power, area, and cost
consumption.
Since the injection of the stimulation current causes the accumulation
of residual charge at the electrode-electrolyte interface, creating a DC
current flow that damages nerve tissue and corrodes the electrodes, the
charge balancing function is required to mitigate the safety issue.
While the active charge balancing (CB) scheme can remove the residual
charge without an additional long discharging period, resulting in fast
stimulation frequency, the passive CB scheme has advantages in terms of
circuit complexity, power, and area consumption [2,3,4]. Given that
the electrical stimulation for seizure suppression is effective in the
low stimulation frequency of 5Hz [5], the passive CB scheme that
minimizes the time constant associated with the resistance of the
passive switches and the impedance of the electrode-tissue interface for
reducing the discharge period can be a feasible alternative to the
active CB scheme.
This work proposes a 64-channel neural stimulator integrated circuit
(IC) for seizure suppression application. The compliance voltage is
maximized by employing a regulated cascode output stage. Given that the
safe range of residual charge, which prevents tissue damage and
electrode corrosion is 15nC [6], we adopt a passive charge balancing
scheme with a bootstrapped switch of low on-resistance. As a result, the
proposed charge-balanced stimulator maintains the residual charge below
1nC within the safety limit at the stimulation frequency of 5Hz, with
in-vivo verification of suppressing seizures in animal tests.
Proposed System Design: Fig. 1 shows the architecture of the
proposed 64-channel neural stimulator system. The overall system
consists of a global 8-bit current digital-to-analog converter (DAC),
level shifter, bandgap reference, digital controller, and 64-channel
stimulator units composed of the output current driver with local 3-bit
DAC and bootstrapped switch for charge balancing as shown in Fig. 1a.
The global 8-bit DAC and local 3-bit DAC can control stimulation current
from 1µA up to 1.8mA. The output driver implemented with a regulated
cascode current source generates bi-phasic pulses capable of stimulating
tissue with an almost complete VDD (5V) compliance range by setting
Vrefp and Vrefn to 4.98V and 0.02V, respectively. Stimulation current
pulse is configured with sequence anodic/cathodic, off, cathodic/anodic,
and discharge periods. The bootstrapped switch shorts the working
electrodes to the reference electrode biased at the voltage of VCM with
low on-resistance at the discharge period. The level shifter changes the
DC level of the digital signal from the digital controller (1.8V) to the
high voltage level for the output current driver (5V). A digital
controller with an SPI slave interface operating in 10MHz configures the
registers for controlling the stimulation parameters of CH (which
channel is activated), Ton (timing information of anodic, off, cathodic,
and discharge pulses), DAC (current of the global DAC), and Amp(current
of the local DAC in stimulation unit). The output driver operates in a
5V supply voltage while the other is under the 1.8V supply voltage with
standard CMOS technology. Fig. 1b shows stimulation pulses generated by
the SPI interface, showing that the MOSI (master output slave input)
command signal triggers the stimulation. All stimulation parameters are
independently configurable, and the SPI commands can configure
mono-phasic, symmetric, and asymmetric bi-phasic stimuli. The pulse
width can be controlled from 1µs up to 1023µs.
Fig. 2 shows the schematic of the output current driver. The impedance
of output node is boosted by a regulated cascode scheme for constant
current injection, regardless of the voltage fluctuation across the
electrode-tissue impedance with wide range of the current amplitude. The
output compliance voltage is maximized through the negative feedback
loop through the OTAs (operating transconductance amplifiers), ensuring
the source node voltages of M1 and M2 are kept as constant as possible
with Vrefp of 4.98V and Vrefn of 0.02V, allowing the high compliance
voltage of 4.9V out of the 5V supply voltage. The 3 bit local DAC
controls the current amplitude of anodic and cathodic pulses from the 8
bit global current DAC.